Evolving wireless communication standards place increasingly stringent performance requirements on the frequency synthesizers that generate RF local oscillator signals for up and down conversion in wireless transceivers. Conventional analog fractional-N PLLs with digital delta-sigma (As) modulation are the current standard for such frequency synthesizers because of their excellent noise and spurious tone performance. See, e.g., T. A. Riley, M. A. Copeland, T. A. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553-559, May 1993. Unfortunately, they require high-performance analog charge pumps and large-area analog filters, so the trends of CMOS technology scaling and increasingly dense system-on-chip integration have created an inhospitable environment for them.
Digital fractional-N PLLs have been developed over the last decade to address this problem. See, e.g., C. Hsu, M. Z. Straayer, M. H. Perrott, “A Low-Noise, Wide-BW 3.6 GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation,” IEEE International Solid-State Circuits Conference, pp. 340-341, February 2008. They avoid large analog loop filters and can tolerate device leakage and low supply voltages which makes them better-suited to highly-scaled CMOS technology than analog PLLs. They are increasingly used in place of analog PLLs as frequency synthesizers. To date, analog PLLs have the best phase error performance, but digital PLLs have the lowest circuit area and are more compatible with highly-scaled CMOS IC technology. Thus, reducing phase error in digital PLLs has been the subject of intensive research and development for over a decade.
A continuing problem in digital PLLs concerns frequency control element (FCE) mismatches. Such FCE mismatches remain a significant source of phase error in high-performance digital PLLs. See, C. Weltin-Wu, E. Familier, and I. Galton, “A linearized model for the design of fractional-N digital PLLs based on dual-mode ring oscillator FDCs,” IEEETrans.Circuits Syst. I, Reg.Papers, vol. 62, no. 8, pp. 2013-2023, August 2015. Prior attempts to address the FCE mismatch problem use an offline calibration technique that requires several minutes to complete. See, O. Eliezer, B. Staszewski, J. Mehta, F. Jabbar, and I. Bashir, “Accurate self-characterization of mismatches in a capacitor array of a digitally-controlled oscillator,” in Proc. IEEE Dallas Circuits Syst. Workshop, October 2010, pp. 17-18; O. Eliezer, B. Staszewski, and S. Vemulapalli, “Digitally controlled oscillator in a 65 nm GSM/EDGE transceiver with built-in compensation for capacitor mismatches,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., June 2011, pp. 5-7.
A digitally controlled oscillator (DCO) is an oscillator whose frequency is controlled by one or more FCEs, each of which is controlled by a 1-bit digital sequence. For instance, each FCE in an LC-based DCO contributes to the DCO's tank a capacitance that takes on one of two values depending on the state of the FCE's input bit. Changing the FCE's input bit increases or decreases the DCO frequency by a fixed frequency step.
The instantaneous frequency of a DCO is given by a fixed offset frequency plus ftune(t), where:
                                                        f              tune                        ⁡                          (              t              )                                =                                    ∑                              i                =                1                                            N                FCE                                      ⁢                                          f                i                            ⁡                              (                t                )                                                    ,                            (        1        )            
NFCE is the number of FCEs in the DCO, and fi(t) is the contribution of the ith FCE to the DCO frequency. Ideally,fi(t)=(bi[mt]−½)Δi,  (2)where bi[m] is the FCE's input bit value (either 0 or 1) over the mth clock interval, mt=└fFCEt┘, fFCE is the clock-rate of the input bit, and Δi is the FCE's frequency step size.
The DCO's input sequence, d[n], represents the ideal value of ftune(t) over the nth clock interval. For example, suppose d[n] is represented as a 16-bit two's complement code where the least significant bit (LSB) represents a DCO frequency step of Δ (e.g., Δ=100 Hz). Then
                                          d            ⁡                          [              n              ]                                =                                    (                                                                    -                                          2                      15                                                        ⁢                                                            d                      15                                        ⁡                                          [                      n                      ]                                                                      +                                                      ∑                                          i                      =                      0                                        14                                    ⁢                                                            2                      i                                        ⁢                                                                  d                        i                                            ⁡                                              [                        n                        ]                                                                                                        )                        ⁢            Δ                          ,                            (        3        )            where di[n], for each i=0, 1, . . . , 15, is the value of the ith bit of the code (either 0 or 1) over the nth clock interval.
Ideally, ftune(t)=d[nt], where nt=└fint┘ and fin is the clock-rate of the DCO input. Equations (1)-(3) with fFCE=fin imply that this can be achieved with a bank of 16 FCEs, where the ith FCE's frequency step size is Δi=2i−1Δ, bi[n]=di−1[n] for i=1, 2, . . . , 15, and b16[n]=1−d15[n].
Unfortunately, in PLL applications that require low phase noise, such as local oscillator synthesis for cellular telephone transceivers, DCOs with minimum frequency steps of tens of Hz are required, but most existing FCEs have minimum frequency steps of tens of kHz or more. A common solution to this problem is described next for an example case in which ftune(t) needs to be controlled in steps of Δ, yet the smallest realizable FCE frequency step size is Δmin=28Δ. In this case, the 8 LSBs of d[n] are said to represent the fractional part of d[n] because they cause DCO frequency steps that are fractions of Δmin, and the 8 most significant bits (MSBs) of d[n] are said to represent the integer part of d[n] because they cause DCO frequency steps that are multiples of Δmin.
The basic approach utilizes two FCE banks: an integer FCE bank controlled by the integer part of d[n], and a fractional FCE bank controlled by the output of an oversampling digital ΔΣ modulator driven by the fractional part of d[n]. The ΔΣ modulator's highpass-shaped quantization noise is lowpass filtered by the DCO, so provided the oversampling rate is sufficiently high, it negligibly contributes to the DCO's phase error.
FIG. 1 shows a specific example in the context of an LC-based DCO, where pt=└ffastt┘, ffast>>fit, and dI[nt] and dF[nt] are the integer and fractional parts of d[nt], respectively. The ffast-clk signal is such that pt changes synchronously with nt, so that nt can be written as a function of pt, i.e.,nt=g(pt).  (4)
In this example g(pt)=└(fin/ffast)pt┘, where ffast/fin is an integer much greater than 1.
It follows from (3) that d[nt]=dI[nt]+dF[nt], where
                                          d            I                    ⁡                      [                          n              t                        ]                          =                              (                                                            -                                      2                    15                                                  ⁢                                                      d                    15                                    ⁡                                      [                                          n                      t                                        ]                                                              +                                                ∑                                      i                    =                    8                                    14                                ⁢                                                      2                    i                                    ⁢                                                            d                      i                                        ⁡                                          [                                              n                        t                                            ]                                                                                            )                    ⁢          Δ                                    (        5        )                        and                                                                            d            F                    ⁡                      [                          n              t                        ]                          =                  Δ          ⁢                                    ∑                              i                =                0                            7                        ⁢                                          2                i                            ⁢                                                                    d                    i                                    ⁡                                      [                                          n                      t                                        ]                                                  .                                                                        (        6        )            
As shown in FIG. 1, dF[nt] is sampled at a rate of ffast by a second-order digital ΔΣ modulator. The ΔΣ modulator's output is a four-level sequence quantized to multiples of Δmin and can be written asyΔΣ[pt]=dF[nt]+eΔΣ[pt],  (7)where eΔΣ[pt] is second-order highpass-shaped quantization noise plus any dither used within the ΔΣ modulator. A thermometer encoder maps yΔΣ[pt] to a 4-bit thermometer code which drives a bank of four FCEs, each with a frequency step of Δmin. It follows from (1), (2) and (7) that the contribution of the fractional FCE bank to the DCO frequency, fF(t), is
                                          f            F                    ⁡                      (            t            )                          =                                            ∑                              i                =                1                            4                        ⁢                                          f                i                            ⁡                              (                t                )                                              =                                                    d                F                            ⁡                              [                                  n                                      t                    ⁢                                                                                                                ]                                      +                                                            e                  ΔΣ                                ⁡                                  [                                      p                    t                                    ]                                            .                                                          (        8        )            
The integer FCE bank is directly driven by dI[nt]. Specifically, the ith FCE, for i=5, 6, . . . , 11, has input bi[nt]=di+3[nt] and frequency step size Δi=2i+3Δ, and the 12th FCE has input b12[nt]=1−d15[nt] and frequency step size Δ12=215Δ. It follows from (1), (2) and (5) that the contribution of the integer FCE bank to the DCO frequency, fI(t), is
                                                        f              I                        ⁡                          (              t              )                                =                                                    ∑                                  i                  =                  5                                12                            ⁢                                                f                  i                                ⁡                                  (                  t                  )                                                      =                                          d                I                            ⁡                              [                                  n                  t                                ]                                                    ,                            (        9        )            where a constant additive term has been omitted.
The contribution of the two FCE banks to the DCO frequency is ftune(t)=fI(t)+fF(t), so (8) and (9) imply thatftune(t)=d[t]+eΔΣ[pt].  (10)
Accordingly, eΔΣ[pt] causes DCO frequency error. The DCO's phase error is the integral of its frequency error, so as mentioned above, a lowpass-filtered version of eΔΣ[pt] appears as a component of the DCO's phase error. Given that eΔΣ[pt] has a highpass-shaped spectrum that peaks at ffast/2, its contribution to the DCO's phase error can be made negligible relative to other sources of phase error if ffast is large enough.
The analysis above presumes that the FCEs are ideal. Unfortunately, non-ideal circuit behavior causes fi(t) to deviate from (2). For example, suppose for now that fi(t) is modeled as ideal except for a static gain error given by αi, i.e.fi(t)=(bi[mt]−½)αiΔi.  (11)
Ideally, αi=1 for i=1, 2, . . . , NFCE, but inevitable component mismatches introduced during fabrication cause αi to deviate from 1.
Repeating the analysis for the example in FIG. 1 with (11) in place of (2) givesftune(t)=αFftune-ideal(t)+eF(t)+eI(t)+(αI−αF)dI[nt],   (12)where ftune-ideal(t) is given by the right side of (10), αF and αI are the averages of αi for i=1, 2, 3, 4 and i=5, 6, . . . , 12, respectively,
                                          e            F                    ⁡                      (            t            )                          =                              ∑                          i              =              1                        4                    ⁢                                    (                                                α                  i                                -                                  α                  F                                            )                        ⁢                          (                                                                    b                    i                                    ⁡                                      [                                          p                      t                                        ]                                                  -                                  1                  ⁢                                      /                                    ⁢                  2                                            )                        ⁢                          Δ              min                                                          (        13        )                        and                                                                            e            I                    ⁡                      (            t            )                          =                              ∑                          i              =              5                        12                    ⁢                                    (                                                α                  i                                -                                  α                  I                                            )                        ⁢                          (                                                                    b                    i                                    ⁡                                      [                                          n                      t                                        ]                                                  -                                  1                  ⁢                                      /                                    ⁢                  2                                            )                        ⁢                                          Δ                i                            .                                                          (        14        )            where ftune-ideal(t) is given by the right side of (10), αF and αI are the averages of αi for i=1, 2, 3, 4 and i=5, 6, . . . , 12, respectively.
Hence, the FCE static gain errors introduce a gain factor, αF, and three additive error terms to ftune(t). The αF gain factor does not significantly degrade performance in typical PLLs. In contrast, as explained next, the three additive error terms in (12) tend to cause spurious tones and increase phase error in PLLs because they are nonlinear functions of d[nt].
The individual bits of d[n], i.e., di[n], for each i=0, 1, . . . , 15, each depend on d[n] but are restricted to values of 0 and 1. Hence, each di[n] is a nonlinear function of d[n]. Nevertheless, they can be combined as in (3) to yield d[n], which implies that multiplying d0[n], d1[n], . . . , d14[n], and d15[n] by 20, 21, . . . , 214, and −215, respectively, and adding the results causes the nonlinear components from the individual bits to cancel each other. Any deviation from a set of scale factors proportional to those mentioned above prevents full cancellation of the nonlinear components. It can be verified from (5), (13) and (14) that eF(t), eI(t), and (αI−αF)dI[nt] are each a function of a subset of the individual bits of d[nt], so they are nonlinear functions of d[nt].
A partial solution to this problem is to replace the thermometer encoder in FIG. 1 with a mismatch-shaping DEM encoder. See, I. Galton, “Why Dynamic-Element-Matching DACs Work,” IEEE Trans. Circuits Syst. II Exp. Briefs, vol. 57, no. 2, pp. 69-74, March 2010. Doing so would cause eF(t) to be replaced by highpass-shaped noise that is free of nonlinear distortion and is uncorrelated with d[nt], so it would be suppressed by the DCO 102 like the ΔΣ quantization noise. Similarly, the integer FCE bank 104 could be modified to accommodate a mismatch-shaping DEM encoder clocked at a rate of fin, which would cause eI(t) to be replaced by shaped noise that is free of nonlinear distortion and is uncorrelated with d[nt]. However, fin □ ffast, less of the shaped noise would be suppressed by the DCO 102. Unfortunately, DEM as described above would not help prevent the last term in (12) from introducing nonlinear distortion because dI[nt] is a non-linear function of d[nt].
The last two terms in (12) increase the phase error in a PLL unless dI[nt] remains constant once the PLL is locked. See, C. Weltin-Wu, G. Zhao, and I. Galton, “A Highly-Digital Frequency Synthesizer Using Ring-Oscillator Frequency-to-Digital Conversion and Noise Cancellation,” IEEE International Solid-State Circuits Conf., pp. 1-3, February 2015. In most published digital PLLs d[n] varies by much less than Δmin when the PLL is locked, and measured results are usually presented for PLL frequencies at which can dI[nt] does not change during the measurement interval. This renders the last two terms in (12) constant, so they do not contribute phase error. Unfortunately, this is not a viable option in practice because DCO center frequency drift caused by flicker noise, voltage and temperature variations, and pulling from external interference cause d[nt] to vary by far more than Δmin over time. For instance, measurement results indicate that the frequency of the DCO presented in [C. Weltin-Wu, G. Zhao, and I. Galton, “A Highly-Digital Frequency Synthesizer Using Ring-Oscillator Frequency-to-Digital Conversion and Noise Cancellation,” IEEE International Solid-State Circuits Conf., pp. 1-3, February 2015] varies by about −200 kHz/° C., which corresponds to ˜7Δmin per degree Celsius. In practice, this causes the digital PLL's phase noise to increase drastically from time to time as d[nt] slowly drifts past integer multiples of Δmin. This issue is sometimes called “spectral breathing” because the phase noise spectrum, as viewed on laboratory measurement equipment, appears to swell up every now and then as if it is taking deep breaths. During these “breaths” the PLL's performance is extremely degraded. Furthermore, when the PLL is used to generate phase or frequency modulated signals, such as a GFSK signal for a Bluetooth transmitter, d[nt] typically varies by more than Δmin, so there are no periods between “breaths” during which the phase noise performance is good.
To address this problem, a single bank of FCEs driven by a ΔΣ modulator and a mismatch-shaping DEM encoder could be used, where the ΔΣ modulator oversamples d[nt] instead of just dF[nt]. The DEM encoder would cause any mismatches among the FCEs to contribute shaped noise instead of nonlinear distortion, and the oversampling would ensure that most of the noise is suppressed by the DCO. Unfortunately, high oversampling ratios would be required in practice, which makes this solution impractical because of the associated high-power consumption